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<div class="title">xi2srx_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for the XI2srx device. </p>
</div></td></tr>
<tr class="memitem:gabd6a5cdc267deb874be64ecff6b93e4b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gabd6a5cdc267deb874be64ecff6b93e4b">XI2S_RX_CORE_VER_OFFSET</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:gabd6a5cdc267deb874be64ecff6b93e4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Version Register.  <a href="group__i2srx.html#gabd6a5cdc267deb874be64ecff6b93e4b">More...</a><br/></td></tr>
<tr class="separator:gabd6a5cdc267deb874be64ecff6b93e4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaab2f8c799ff6de247d102de9eca1578c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gaab2f8c799ff6de247d102de9eca1578c">XI2S_RX_CORE_CFG_OFFSET</a>&#160;&#160;&#160;0x04</td></tr>
<tr class="memdesc:gaab2f8c799ff6de247d102de9eca1578c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Configuration Register.  <a href="group__i2srx.html#gaab2f8c799ff6de247d102de9eca1578c">More...</a><br/></td></tr>
<tr class="separator:gaab2f8c799ff6de247d102de9eca1578c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa79a92debd04aa3b8f9866869fcee2ea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gaa79a92debd04aa3b8f9866869fcee2ea">XI2S_RX_CORE_CTRL_OFFSET</a>&#160;&#160;&#160;0x08</td></tr>
<tr class="memdesc:gaa79a92debd04aa3b8f9866869fcee2ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Control Register.  <a href="group__i2srx.html#gaa79a92debd04aa3b8f9866869fcee2ea">More...</a><br/></td></tr>
<tr class="separator:gaa79a92debd04aa3b8f9866869fcee2ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d9730105131e980b1b2ca3996969f31"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga9d9730105131e980b1b2ca3996969f31">XI2S_RX_IRQCTRL_OFFSET</a>&#160;&#160;&#160;0x10</td></tr>
<tr class="memdesc:ga9d9730105131e980b1b2ca3996969f31"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Control Register.  <a href="group__i2srx.html#ga9d9730105131e980b1b2ca3996969f31">More...</a><br/></td></tr>
<tr class="separator:ga9d9730105131e980b1b2ca3996969f31"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga10ebd12832c0df2b25d86e1c426917a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga10ebd12832c0df2b25d86e1c426917a2">XI2S_RX_IRQSTS_OFFSET</a>&#160;&#160;&#160;0x14</td></tr>
<tr class="memdesc:ga10ebd12832c0df2b25d86e1c426917a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Register.  <a href="group__i2srx.html#ga10ebd12832c0df2b25d86e1c426917a2">More...</a><br/></td></tr>
<tr class="separator:ga10ebd12832c0df2b25d86e1c426917a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad10e1d11d2c50b2111dd3f8a4dd26389"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gad10e1d11d2c50b2111dd3f8a4dd26389">XI2S_RX_TMR_CTRL_OFFSET</a>&#160;&#160;&#160;0x20</td></tr>
<tr class="memdesc:gad10e1d11d2c50b2111dd3f8a4dd26389"><td class="mdescLeft">&#160;</td><td class="mdescRight">XI2S Timing Control Register.  <a href="group__i2srx.html#gad10e1d11d2c50b2111dd3f8a4dd26389">More...</a><br/></td></tr>
<tr class="separator:gad10e1d11d2c50b2111dd3f8a4dd26389"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc668d400426098bae3149a9fc4c094f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gacc668d400426098bae3149a9fc4c094f">XI2S_RX_CH01_OFFSET</a>&#160;&#160;&#160;0x30</td></tr>
<tr class="memdesc:gacc668d400426098bae3149a9fc4c094f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 0/1 Control Register.  <a href="group__i2srx.html#gacc668d400426098bae3149a9fc4c094f">More...</a><br/></td></tr>
<tr class="separator:gacc668d400426098bae3149a9fc4c094f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d7fe447197f14d38b515caa072893b7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga7d7fe447197f14d38b515caa072893b7">XI2S_RX_CH23_OFFSET</a>&#160;&#160;&#160;0x34</td></tr>
<tr class="memdesc:ga7d7fe447197f14d38b515caa072893b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 2/3 Control Register.  <a href="group__i2srx.html#ga7d7fe447197f14d38b515caa072893b7">More...</a><br/></td></tr>
<tr class="separator:ga7d7fe447197f14d38b515caa072893b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga29d0c7f997d393d644e6374ea70e6ac2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga29d0c7f997d393d644e6374ea70e6ac2">XI2S_RX_CH45_OFFSET</a>&#160;&#160;&#160;0x38</td></tr>
<tr class="memdesc:ga29d0c7f997d393d644e6374ea70e6ac2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 4/5 Control Register.  <a href="group__i2srx.html#ga29d0c7f997d393d644e6374ea70e6ac2">More...</a><br/></td></tr>
<tr class="separator:ga29d0c7f997d393d644e6374ea70e6ac2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae40a3a7ebb7cee1e4a3d935e6b51569f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gae40a3a7ebb7cee1e4a3d935e6b51569f">XI2S_RX_CH67_OFFSET</a>&#160;&#160;&#160;0x3C</td></tr>
<tr class="memdesc:gae40a3a7ebb7cee1e4a3d935e6b51569f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 6/7 Control Register.  <a href="group__i2srx.html#gae40a3a7ebb7cee1e4a3d935e6b51569f">More...</a><br/></td></tr>
<tr class="separator:gae40a3a7ebb7cee1e4a3d935e6b51569f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaef854c082d18fb31d75d15c23aa7fab5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gaef854c082d18fb31d75d15c23aa7fab5">XI2S_RX_AES_CHSTS0_OFFSET</a>&#160;&#160;&#160;0x50</td></tr>
<tr class="memdesc:gaef854c082d18fb31d75d15c23aa7fab5"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 0 Register.  <a href="group__i2srx.html#gaef854c082d18fb31d75d15c23aa7fab5">More...</a><br/></td></tr>
<tr class="separator:gaef854c082d18fb31d75d15c23aa7fab5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6eb6685030ce7a4097e2d26591026109"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga6eb6685030ce7a4097e2d26591026109">XI2S_RX_AES_CHSTS1_OFFSET</a>&#160;&#160;&#160;0x54</td></tr>
<tr class="memdesc:ga6eb6685030ce7a4097e2d26591026109"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 1 Register.  <a href="group__i2srx.html#ga6eb6685030ce7a4097e2d26591026109">More...</a><br/></td></tr>
<tr class="separator:ga6eb6685030ce7a4097e2d26591026109"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a5e64ec439b371f7dbb7795796ea525"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga4a5e64ec439b371f7dbb7795796ea525">XI2S_RX_AES_CHSTS2_OFFSET</a>&#160;&#160;&#160;0x58</td></tr>
<tr class="memdesc:ga4a5e64ec439b371f7dbb7795796ea525"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 2 Register.  <a href="group__i2srx.html#ga4a5e64ec439b371f7dbb7795796ea525">More...</a><br/></td></tr>
<tr class="separator:ga4a5e64ec439b371f7dbb7795796ea525"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5aec8ad439da8047b7e2406680091bb3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga5aec8ad439da8047b7e2406680091bb3">XI2S_RX_AES_CHSTS3_OFFSET</a>&#160;&#160;&#160;0x5C</td></tr>
<tr class="memdesc:ga5aec8ad439da8047b7e2406680091bb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 3 Register.  <a href="group__i2srx.html#ga5aec8ad439da8047b7e2406680091bb3">More...</a><br/></td></tr>
<tr class="separator:ga5aec8ad439da8047b7e2406680091bb3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga64228e861649cfca19122186738890c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga64228e861649cfca19122186738890c3">XI2S_RX_AES_CHSTS4_OFFSET</a>&#160;&#160;&#160;0x60</td></tr>
<tr class="memdesc:ga64228e861649cfca19122186738890c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 4 Register.  <a href="group__i2srx.html#ga64228e861649cfca19122186738890c3">More...</a><br/></td></tr>
<tr class="separator:ga64228e861649cfca19122186738890c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gada5ad0f01fc6b245bc58fb0ac66f3672"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gada5ad0f01fc6b245bc58fb0ac66f3672">XI2S_RX_AES_CHSTS5_OFFSET</a>&#160;&#160;&#160;0x64</td></tr>
<tr class="memdesc:gada5ad0f01fc6b245bc58fb0ac66f3672"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 5 Register.  <a href="group__i2srx.html#gada5ad0f01fc6b245bc58fb0ac66f3672">More...</a><br/></td></tr>
<tr class="separator:gada5ad0f01fc6b245bc58fb0ac66f3672"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Core Configuration Register masks and shifts</div></td></tr>
<tr class="memitem:ga386baab9d9d9e77e9569f78f8535c79a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga386baab9d9d9e77e9569f78f8535c79a">XI2S_RX_REG_CFG_MSTR_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga386baab9d9d9e77e9569f78f8535c79a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is XI2S Master bit shift.  <a href="group__i2srx.html#ga386baab9d9d9e77e9569f78f8535c79a">More...</a><br/></td></tr>
<tr class="separator:ga386baab9d9d9e77e9569f78f8535c79a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc9bad93a6ce59caa98a961eca5180fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gacc9bad93a6ce59caa98a961eca5180fd">XI2S_RX_REG_CFG_MSTR_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga386baab9d9d9e77e9569f78f8535c79a">XI2S_RX_REG_CFG_MSTR_SHIFT</a>)</td></tr>
<tr class="memdesc:gacc9bad93a6ce59caa98a961eca5180fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is XI2S Master mask.  <a href="group__i2srx.html#gacc9bad93a6ce59caa98a961eca5180fd">More...</a><br/></td></tr>
<tr class="separator:gacc9bad93a6ce59caa98a961eca5180fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga33b447ccf86e1d8e207cd5b04cc0e0bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga33b447ccf86e1d8e207cd5b04cc0e0bd">XI2S_RX_REG_CFG_NUM_CH_SHIFT</a>&#160;&#160;&#160;(8)</td></tr>
<tr class="memdesc:ga33b447ccf86e1d8e207cd5b04cc0e0bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum number of channels bit shift.  <a href="group__i2srx.html#ga33b447ccf86e1d8e207cd5b04cc0e0bd">More...</a><br/></td></tr>
<tr class="separator:ga33b447ccf86e1d8e207cd5b04cc0e0bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6f0aaac08ca351e2389bbe04a8b6a87f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga6f0aaac08ca351e2389bbe04a8b6a87f">XI2S_RX_REG_CFG_NUM_CH_MASK</a>&#160;&#160;&#160;(0xF &lt;&lt; XI2S_RX_REG_CFG_NUM_CH_SHIFT)</td></tr>
<tr class="memdesc:ga6f0aaac08ca351e2389bbe04a8b6a87f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum number of channels mask.  <a href="group__i2srx.html#ga6f0aaac08ca351e2389bbe04a8b6a87f">More...</a><br/></td></tr>
<tr class="separator:ga6f0aaac08ca351e2389bbe04a8b6a87f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9cf777ebbfe32e3744fc3ec6e7b0b439"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga9cf777ebbfe32e3744fc3ec6e7b0b439">XI2S_RX_REG_CFG_DWDTH_SHIFT</a>&#160;&#160;&#160;(16)</td></tr>
<tr class="memdesc:ga9cf777ebbfe32e3744fc3ec6e7b0b439"><td class="mdescLeft">&#160;</td><td class="mdescRight">XI2S Data Width bit shift.  <a href="group__i2srx.html#ga9cf777ebbfe32e3744fc3ec6e7b0b439">More...</a><br/></td></tr>
<tr class="separator:ga9cf777ebbfe32e3744fc3ec6e7b0b439"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e6c0504d9ddf7ecb2301b76815d7fc4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga8e6c0504d9ddf7ecb2301b76815d7fc4">XI2S_RX_REG_CFG_DWDTH_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga9cf777ebbfe32e3744fc3ec6e7b0b439">XI2S_RX_REG_CFG_DWDTH_SHIFT</a>)</td></tr>
<tr class="memdesc:ga8e6c0504d9ddf7ecb2301b76815d7fc4"><td class="mdescLeft">&#160;</td><td class="mdescRight">XI2S Data Width mask.  <a href="group__i2srx.html#ga8e6c0504d9ddf7ecb2301b76815d7fc4">More...</a><br/></td></tr>
<tr class="separator:ga8e6c0504d9ddf7ecb2301b76815d7fc4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Core Control Register masks and shifts</div></td></tr>
<tr class="memitem:ga2b6fec3d30ffb6d6e75686cbd6050d05"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga2b6fec3d30ffb6d6e75686cbd6050d05">XI2S_RX_REG_CTRL_EN_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga2b6fec3d30ffb6d6e75686cbd6050d05"><td class="mdescLeft">&#160;</td><td class="mdescRight">Module Enable bit shift.  <a href="group__i2srx.html#ga2b6fec3d30ffb6d6e75686cbd6050d05">More...</a><br/></td></tr>
<tr class="separator:ga2b6fec3d30ffb6d6e75686cbd6050d05"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72d3a8ea524c40940140512a982fb910"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga72d3a8ea524c40940140512a982fb910">XI2S_RX_REG_CTRL_EN_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga2b6fec3d30ffb6d6e75686cbd6050d05">XI2S_RX_REG_CTRL_EN_SHIFT</a>)</td></tr>
<tr class="memdesc:ga72d3a8ea524c40940140512a982fb910"><td class="mdescLeft">&#160;</td><td class="mdescRight">Module Enable mask.  <a href="group__i2srx.html#ga72d3a8ea524c40940140512a982fb910">More...</a><br/></td></tr>
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<tr class="memitem:gac9e9f8391850f0ca4407e7fda7b3c7d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gac9e9f8391850f0ca4407e7fda7b3c7d6">XI2S_RX_REG_CTRL_JFE_SHIFT</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:gac9e9f8391850f0ca4407e7fda7b3c7d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Justification Enable or Disable shift.  <a href="group__i2srx.html#gac9e9f8391850f0ca4407e7fda7b3c7d6">More...</a><br/></td></tr>
<tr class="separator:gac9e9f8391850f0ca4407e7fda7b3c7d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4bed9d26f96c101a80fdeb5e16c61882"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga4bed9d26f96c101a80fdeb5e16c61882">XI2S_RX_REG_CTRL_JFE_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#gac9e9f8391850f0ca4407e7fda7b3c7d6">XI2S_RX_REG_CTRL_JFE_SHIFT</a>)</td></tr>
<tr class="memdesc:ga4bed9d26f96c101a80fdeb5e16c61882"><td class="mdescLeft">&#160;</td><td class="mdescRight">Justification Enable or Disable mask.  <a href="group__i2srx.html#ga4bed9d26f96c101a80fdeb5e16c61882">More...</a><br/></td></tr>
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<tr class="memitem:gaf733f45be6a7f7c489c2ef5a0faf1cc1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gaf733f45be6a7f7c489c2ef5a0faf1cc1">XI2S_RX_REG_CTRL_LORJF_SHIFT</a>&#160;&#160;&#160;(2)</td></tr>
<tr class="memdesc:gaf733f45be6a7f7c489c2ef5a0faf1cc1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Left or Right Justification shift.  <a href="group__i2srx.html#gaf733f45be6a7f7c489c2ef5a0faf1cc1">More...</a><br/></td></tr>
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<tr class="memitem:gae1e05f03cc894aaa4e5bf213460eeb43"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gae1e05f03cc894aaa4e5bf213460eeb43">XI2S_RX_REG_CTRL_LORJF_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#gaf733f45be6a7f7c489c2ef5a0faf1cc1">XI2S_RX_REG_CTRL_LORJF_SHIFT</a>)</td></tr>
<tr class="memdesc:gae1e05f03cc894aaa4e5bf213460eeb43"><td class="mdescLeft">&#160;</td><td class="mdescRight">Left or Right Justification mask.  <a href="group__i2srx.html#gae1e05f03cc894aaa4e5bf213460eeb43">More...</a><br/></td></tr>
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<tr class="memitem:ga2a4b4b0ed331511eea0872abe6d1a008"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga2a4b4b0ed331511eea0872abe6d1a008">XI2S_RX_REG_CTRL_LATCH_CHSTS_SHIFT</a>&#160;&#160;&#160;(16)</td></tr>
<tr class="memdesc:ga2a4b4b0ed331511eea0872abe6d1a008"><td class="mdescLeft">&#160;</td><td class="mdescRight">Latch AES Channel Status bit shift.  <a href="group__i2srx.html#ga2a4b4b0ed331511eea0872abe6d1a008">More...</a><br/></td></tr>
<tr class="separator:ga2a4b4b0ed331511eea0872abe6d1a008"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab1cb52ffff197179ecb2453f3b055f2e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gab1cb52ffff197179ecb2453f3b055f2e">XI2S_RX_REG_CTRL_LATCH_CHSTS_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga2a4b4b0ed331511eea0872abe6d1a008">XI2S_RX_REG_CTRL_LATCH_CHSTS_SHIFT</a>)</td></tr>
<tr class="memdesc:gab1cb52ffff197179ecb2453f3b055f2e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Latch AES Channel Status mask.  <a href="group__i2srx.html#gab1cb52ffff197179ecb2453f3b055f2e">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Interrupt masks and shifts</div></td></tr>
<tr class="memitem:gaeeff2f78e8d4799f14b13f5dd74f07ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gaeeff2f78e8d4799f14b13f5dd74f07ac">XI2S_RX_INTR_AES_BLKCMPLT_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:gaeeff2f78e8d4799f14b13f5dd74f07ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Block Complete Interrupt bit shift.  <a href="group__i2srx.html#gaeeff2f78e8d4799f14b13f5dd74f07ac">More...</a><br/></td></tr>
<tr class="separator:gaeeff2f78e8d4799f14b13f5dd74f07ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa37ac42887b7ca3d17a5a48af43c3d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gafa37ac42887b7ca3d17a5a48af43c3d1">XI2S_RX_INTR_AES_BLKCMPLT_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#gaeeff2f78e8d4799f14b13f5dd74f07ac">XI2S_RX_INTR_AES_BLKCMPLT_SHIFT</a>)</td></tr>
<tr class="memdesc:gafa37ac42887b7ca3d17a5a48af43c3d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Block Complete Interrupt mask.  <a href="group__i2srx.html#gafa37ac42887b7ca3d17a5a48af43c3d1">More...</a><br/></td></tr>
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<tr class="memitem:ga12970ee31e47fcfe72564f65923519ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga12970ee31e47fcfe72564f65923519ff">XI2S_RX_INTR_AUDOVRFLW_SHIFT</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:ga12970ee31e47fcfe72564f65923519ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Overflow Detected Interrupt bit shift.  <a href="group__i2srx.html#ga12970ee31e47fcfe72564f65923519ff">More...</a><br/></td></tr>
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<tr class="memitem:gacf7d542116f93c176f729165c0c0ab46"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gacf7d542116f93c176f729165c0c0ab46">XI2S_RX_INTR_AUDOVRFLW_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga12970ee31e47fcfe72564f65923519ff">XI2S_RX_INTR_AUDOVRFLW_SHIFT</a>)</td></tr>
<tr class="memdesc:gacf7d542116f93c176f729165c0c0ab46"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Overflow Detected Interrupt mask.  <a href="group__i2srx.html#gacf7d542116f93c176f729165c0c0ab46">More...</a><br/></td></tr>
<tr class="separator:gacf7d542116f93c176f729165c0c0ab46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ff2b2e7bc857175d47e3b396337c3c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga6ff2b2e7bc857175d47e3b396337c3c8">XI2S_RX_GINTR_EN_SHIFT</a>&#160;&#160;&#160;(31)</td></tr>
<tr class="memdesc:ga6ff2b2e7bc857175d47e3b396337c3c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Enable bit shift.  <a href="group__i2srx.html#ga6ff2b2e7bc857175d47e3b396337c3c8">More...</a><br/></td></tr>
<tr class="separator:ga6ff2b2e7bc857175d47e3b396337c3c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7089f6d78ab940b47ac4e63cc9de876d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga7089f6d78ab940b47ac4e63cc9de876d">XI2S_RX_GINTR_EN_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2srx.html#ga6ff2b2e7bc857175d47e3b396337c3c8">XI2S_RX_GINTR_EN_SHIFT</a>)</td></tr>
<tr class="memdesc:ga7089f6d78ab940b47ac4e63cc9de876d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Enable mask.  <a href="group__i2srx.html#ga7089f6d78ab940b47ac4e63cc9de876d">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">XI2S Timing Control Register masks and shifts</div></td></tr>
<tr class="memitem:gab3b615049121f07d4a919c3a36866598"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gab3b615049121f07d4a919c3a36866598">XI2S_RX_REG_TMR_SCLKDIV_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:gab3b615049121f07d4a919c3a36866598"><td class="mdescLeft">&#160;</td><td class="mdescRight">SClk Divider bit shift.  <a href="group__i2srx.html#gab3b615049121f07d4a919c3a36866598">More...</a><br/></td></tr>
<tr class="separator:gab3b615049121f07d4a919c3a36866598"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a6e25d96079222ab136c05ab1040bf6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga0a6e25d96079222ab136c05ab1040bf6">XI2S_RX_REG_TMR_SCLKDIV_MASK</a>&#160;&#160;&#160;(0xF &lt;&lt; XI2S_RX_REG_TMR_SCLKDIV_SHIFT)</td></tr>
<tr class="memdesc:ga0a6e25d96079222ab136c05ab1040bf6"><td class="mdescLeft">&#160;</td><td class="mdescRight">SClk Divider mask.  <a href="group__i2srx.html#ga0a6e25d96079222ab136c05ab1040bf6">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Audio Channel Control Register masks and shifts</div></td></tr>
<tr class="memitem:gac24b161236882834c75e99865405aed4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gac24b161236882834c75e99865405aed4">XI2S_RX_REG_CHCTRL_CHMUX_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:gac24b161236882834c75e99865405aed4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel MUX bit shift.  <a href="group__i2srx.html#gac24b161236882834c75e99865405aed4">More...</a><br/></td></tr>
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<tr class="memitem:ga55cd99e10d5e57674583e973d07cd1f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga55cd99e10d5e57674583e973d07cd1f3">XI2S_RX_REG_CHCTRL_CHMUX_MASK</a>&#160;&#160;&#160;(0x7 &lt;&lt; XI2S_RX_REG_CHCTRL_CHMUX_SHIFT)</td></tr>
<tr class="memdesc:ga55cd99e10d5e57674583e973d07cd1f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel MUX mask.  <a href="group__i2srx.html#ga55cd99e10d5e57674583e973d07cd1f3">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Register access macro definition</div></td></tr>
<tr class="memitem:ga09a5bac7db972eedb59f8a333b9ab962"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga09a5bac7db972eedb59f8a333b9ab962">XI2s_Rx_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:ga09a5bac7db972eedb59f8a333b9ab962"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Operations.  <a href="group__i2srx.html#ga09a5bac7db972eedb59f8a333b9ab962">More...</a><br/></td></tr>
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<tr class="memitem:gadab8698c5b4c02161f42cfc947c5d1b2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gadab8698c5b4c02161f42cfc947c5d1b2">XI2s_Rx_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:gadab8698c5b4c02161f42cfc947c5d1b2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Operations.  <a href="group__i2srx.html#gadab8698c5b4c02161f42cfc947c5d1b2">More...</a><br/></td></tr>
<tr class="separator:gadab8698c5b4c02161f42cfc947c5d1b2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7f13e37d826cfd786b54f7ad04c0fd3c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#ga7f13e37d826cfd786b54f7ad04c0fd3c">XI2s_Rx_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;<a class="el" href="group__i2srx.html#ga09a5bac7db972eedb59f8a333b9ab962">XI2s_Rx_In32</a>((BaseAddress) + ((u32)RegOffset))</td></tr>
<tr class="memdesc:ga7f13e37d826cfd786b54f7ad04c0fd3c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads a value from a XI2s Receiver register.  <a href="group__i2srx.html#ga7f13e37d826cfd786b54f7ad04c0fd3c">More...</a><br/></td></tr>
<tr class="separator:ga7f13e37d826cfd786b54f7ad04c0fd3c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac98a6dde12e4efc76872f80b47fe641f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2srx.html#gac98a6dde12e4efc76872f80b47fe641f">XI2s_Rx_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;<a class="el" href="group__i2srx.html#gadab8698c5b4c02161f42cfc947c5d1b2">XI2s_Rx_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:gac98a6dde12e4efc76872f80b47fe641f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes a value to a XI2s Receiver register.  <a href="group__i2srx.html#gac98a6dde12e4efc76872f80b47fe641f">More...</a><br/></td></tr>
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